The present invention relates to the processing of integrated circuits and, more particularly, to the use of a dielectric barrier material under a dielectric passivating material in order to effectively process oversized vias in multilayer metalization structures.
Previous methods of making via interconnections in integrated circuits required placing a via opening totally within a pad of an underlying metal. This metal acted as a stop for the etching of the passivating dielectric. The pad had to be large enough to facilitate easy alignment of the dielectric lithographic pattern to the metal pattern and to allow for overetching of the dielectric material.
Integrated circuits formed in accordance with the present invention do not require a pad of underlying metal but allow for the via to be oversized. That is, the via opening can overlap the metalization.
Integrated circuits are designed according to applicable minimum and maximum layout rules. In metalization layers, the spacing of metal features is determined by the smallest gap that can be patterned into the metal. In prior art via approaches, the pad-to-pad spacing determined the separation of metal runners. Using an oversized via, the spacing between metal runners can be reduced to the minimum metal-to-metal space that can be patterned.
For large scale integrated circuits, one of the major limiting factors of circuit densities is the spacing between thin film metalization interconnects. This limitation exists for every layer of metal on an integrated circuit; therefore elimination of metal via pads increases circuit densities.